Embodiments relate to an electrical device, such as a semiconductor device, and methods of manufacturing the same. Some embodiments relate to a semiconductor device having a shallow trench isolation (STI) layer and a method for manufacturing the STI layer.
Recently, techniques to manufacture a semiconductor device have been investigated due to their expanded use in a wide field of applications. Research and development has sought to increase integration density of a semiconductor device, which continues to improve at a relatively high rate. Due to the increase in integration density of a semiconductor device, research related to fine processing technique based miniaturization of a semiconductor device has also advanced. For example, techniques to reduce an isolation layer, which may operate to separate elements and integrate the elements in a semiconductor device, are increasing.
A Local Oxidation of Silicon (LOCOS) technique may be used as an isolation technique. In a LOCOS technique, a thick oxide layer may be selectively grown over a semiconductor substrate to form an isolation layer. However, this technique may fail to reduce the width of an isolation layer since an oxide layer may be formed over a portion where lateral diffusion of an isolation layer should be avoided. Thus, in a semiconductor device where element manufacturing may be on a submicron scale, the LOCOS technique may not be applicable.
A shallow trench isolation (STI) technique may be used as an isolation technique. A relatively shallow trench may be formed over a semiconductor substrate by an etching process in a STI technique, and an insulating material may be buried in the shallow trench. Thus, a relatively smaller isolation region using a STI technique may be achieved compared to a LOCOS technique. FIG. 1A to FIG. 1F are cross sectional views of a process to manufacture a shallow trench isolation layer of a semiconductor device.
A pad oxide layer and a hard mask layer, for example a silicon nitride (e.g., Si3N4) layer, may be formed over a substrate such as silicon semiconductor substrate 100 illustrated in FIG. 1A. Referring to FIG. 1B, semiconductor substrate 100 may be etched, for example dry etched, to a certain depth using a pattern of a hard mask layer and/or a pad oxide layer. The depth may be between approximately 3000 Å to 5000 Å, and may form a shallow trench. A shallow trench isolation (STI) layer may then be formed therein.
Referring to FIG. 1C, liner insulating layer 102, for example a silicon oxide (e.g., SiO2) layer, may be substantially thinly formed over silicon substrate 100 having a shallow trench formed thereover. While forming the STI layer, for example in the case of a narrow width transistor, a transistor characteristic at a middle aspect ratio (for example, W/L=0.25/1) shows an abnormal phenomenon resulting from Si stress. Therefore, a liner insulating layer may be used to address the abnormal phenomenon.
Referring to FIG. 1D, gap-fill insulating layer 104, for example a silicon oxide (e.g., SiO2) layer and/or a tetraetylorthosilicate (TEOS) layer, may be deposited to bury a shallow trench. Gap-fill insulating layer 104 and liner insulating layer 102 may be partially removed when the hard mask layer is exposed, for example by Chemical Mechanical Polishing (CMP), to make a planar surface. Referring to FIG. 1E, liner insulating layer 102 and gap-fill insulating layer 104 may be formed as illustrated after planarization. The hard mask layer may be used as a lower nitride layer and may operate as an etching stop layer for gap-fill insulating layer 104.
Referring to FIG. 1F, the hard mask layer may be removed, for example using phosphoric acid, and the pad oxide layer may be partly removed, for example by a cleansing process. A gate layer 106 may then be formed, thereby completing a shallow trench isolation layer. However, since a CMP process is conducted over a gap-fill insulating layer and a liner insulating layer until a hard mask layer is exposed, a dishing effect may occur when the CMP process is conducted over the gap-fill insulating layer and the liner insulating layer.
A dishing effect may cause problems at bridge or pattern formation in subsequent processes, such as a gate layer forming process. Thus, there is a need for a semiconductor device having a shallow trench isolation (STI) layer and a method for manufacturing the STI layer, which may lack and/or may prevent a dishing effect, and/or which may maintain a narrow width characteristic of a transistor.